Hey guys! Here’s some questions on Some Questions on Computer System Architecture based on basics of CSA such as Von Newmann’s Architecture, registers, memory and lot’s of other cool stuff.

So let’s get straight into it!

Q1. Using Full adder, design a 6-bit adder/ subtractor circuit.

Solution: A full adder circuit is an adder circuit which takes 3 inputs and produces 2 outputs. Here’s what a 6-bit adder/subtractor circuit looks like

Q2. Construct a common bus system for four 8-bit register using multiplexer.

Solution: For the solution of this question we have to follow the below condition:

“For k register of n bits, each produce an n– line common bus.
The number of multiplexer needed is equal to n( no of bits in each register)
The size of each multiplexer must be k ×1″

A multiplexer is a combinational circuit which have many data inputs and single output depending on control or select inputs. To construct a common bus system using an 8-bit register we have to use an 8-bit multiplexer.​ An 8-bit multiplexer have 8 inputs and 3 select lines(control inputs). Here’s what a common bus system for four 8-bit register using multiplexer looks like

To download HD image for Question 1 and Question 2

Q3. What is the need of Bus arbitration? How can Bus arbitration be implemented using different methods?

Solution:  A device that initiates data transfers on the bus at any given time is called a bus master. Bus arbitration is a process by which the next device becomes the bus controller by transferring bus mastership to another bus. This process is required when there are two or more processes requesting the bus service.

Different methods through which bus arbitration can be implemented are:

  1. Daisy Chaining method: The daisy chain method gives the highest priority to the device that receives the interrupt acknowledge signal from the CPU. The farther the device is from the first position, the lower is its priority.
  2. Polling or Rotating Priority method: A polling procedure is used to identify the highest-priority source by software means. In this method, there is one common branch address for all interrupts. The program that takes care of interrupts begins at the branch address and polls the interrupt sources in sequence.
  3. Fixed priority or Independent Request method: In this, each master has a separate pair of bus request and bus grant lines and each pair has a priority assigned to it.  The built-in priority decoder within the controller selects the highest priority request and asserts the corresponding bus grant signal.

Q4. An 8 bit register contains the binary value AR=11010110 BR=01011110 What is the register. Value after following micro-operation.

A. Arithmetic shift left & right

Solution: Arithmetic shift left: AR =10101100 BR = 10111100

Arithmetic shift right: AR = 11101011 BR = 00101111

B. Circular shift left & right

Solution: Circular shift left: AR = 10101101 BR = 10111100

Circular shift right: AR = 01101011 BR = 00101111

C. Logical shift left & right

Solution: Logical shift left: AR = 10101100 BR = 10111100

Logical shift right: AR = 01101011 BR = 00101111

D. BR← AR ^ BR

Solution: Here ‘^’ symbol means ‘AND’ operation, which means BR = AR AND BR and the result comes out to be BR = 1010110.

Q5. What is micro-operation. Discuss different micro-operation in detail.

Solution: Micro-operations are the atomic operation that involves transfer between registers, transfer between registers and external bus, or a simple ALU (Arithmetic logical unit) operation.

The micro-operations in digital computers are of 4 types:

  1. Register transfer micro-operations : These type of micro operations are used to transfer from one register to another binary information.
  2. Arithmetic micro-operations: These micro-operations are used to perform on numeric data stored in the registers some arithmetic operations.
  3. Logic micro-operations: These micro operations are used to perform bit style operations / manipulations on non numeric data.
  4. Shift micro operations: As their name suggests they are used to perform shift operations in data store in registers.

Q6. Show the H/W implementation to the given statement
xy : A←B , B←A

Solution: As the above statement is separated by commas, this means there is a simultaneous occurrence of 2 micro-operations.

Q7. A computer uses RAM chip of 1024 X 1 capacity.
(a) How many chips are needed, and how should their address lines be connected to provide a memory capacity of 1024 bytes?
(b) How many chips are needed to provide a memory capacity of 16K bytes? Explain in words how the chips are to be connected to the address bus?

a) The computer uses a 1-bit RAM chip that provides a memory capacity of 1024*1=1024 bits. To provide a memory capacity of 1024 bytes 8 chips are needed with 10 address lines connected in parallel as 1 byte = 8bits and 210 = 1024.

b)16 × 8 = 128 chips. Use 14 address lines (16 k = 214)
10 lines specify the chip address
4 lines are decoded into 16 chip-select inputs.

Q8. What is cache memory? Calculate the average effective access time of a system having two levels of memory hierarchy: a cache memory, a semiconductor main memory. The access times of these memories are 10 ns, 100 ns respectively. The cache hit ratio is .99.

Solution: Cache Memory is small, high-speed RAM buffer located between CPU and main memory.The main purpose of cache memory is to accelerate the computer while keeping the computer’s price low.

To calculate the avg. access time,

T1 =10ns (access time of cache memory)

T2 = 100ns (access time of main memory)

HR = 0.99 (Hit ratio)

MR =1 – 0.99 = 0.01 (Miss Ratio)

AAT = HR * T1 + MR * (T1 + T2)

AAT = 0.99 * 10 + 0.01 * (100 + 10) = 11ns

Q9. Write an assembly language program to evaluate the arithmetic statement
(i) X= (A+BC)/ (D-E * F+G*H)
Using general register type computer with 3 address instruction.
Using Stack based computer with zero address instruction.

Solution: A. Using general register type computer with 3 address instruction.

MULR1,B,CR1←M[B]*M[C]
ADDR1,R1,AR1←R1+M[A]
MULR2,E,FR2←M[E]*M[F]
SUBR2,D,R2R2←[D]-R2
MULR3,G,HR3←M[G]*M[H]
ADDR2,R2,R3R2←R2+R3
DIVX,R1,R2X←R1/R2

B. Using Stack based computer with zero address instruction.

Post-fix expression for the arithmetic expression : ABC*+DEF*-GH*+/

PUSH ATOS←A
PUSH BTOS←B
PUSH CTOS←C
MULTOS←B*C
ADDTOS←A+B*C
PUSH DTOS←D
PUSH ETOS←E
PUSH FTOS←F
MULTOS←E*F
SUBTOS←D*E-F
PUSH GTOS←G
PUSH HTOS←H
MULTOS←G*H
ADDTOS←D-E*F+G*H
DIVTOS←(A+B*C)/(D*E*F+G*H)
POP X

Q10. Discuss why interfacing is used in digital computers? Explain the salient features of a device interface.

Solution: Interfacing is the method of connecting or linking together one device, especially a computer or micro-controller with another allowing us to design or adapt the output and input configurations of the two electronic devices so that they can work together.

Salient features of device interface:

  • provides a consistent discovery mechanism for devices based on shared characteristics
  • Provides standardized naming
  • Support for custom properties and settings
  • Provides a system managed path for I/O Requests
  • Provides notification of the availability of new interfaces
  • Available to kernel-mode components and user-mode applications

Q11. Discuss the DMA? Why is the read and write control lines in a DMA controller bidirectional?

Solution: Direct memory access (DMA) is a method that allows an input/output (I/O) device to send or receive data directly to or from the main memory, bypassing the CPU to speed up memory operations. The process is managed by a chip known as a DMA controller (DMAC). Here’s a block diagram representation of DMA.

DMA (Direct Memory Access)

The read and write control lines running through the data buses have control signals. The microprocessor can read data from memory or write data to the memory so the data buses are bidirectional. One direction is needed to write the data while another direction is required for the read command to fetch the data.

Q12. Differentiate between synchronous and asynchronous data transfer schemes?

Solution: In the Synchronous Data Transfer Scheme, a clock is present in control lines. This scheme follows a fixed protocol for communication that is relative to the clock. The advantage of this scheme is it involves very little logic and runs very fast. But in this scheme, every device on the bus must run on the same clock rate.

In Asynchronous Data Transfer Scheme, no clock is present in control lines. This scheme can accommodate a wide range of devices and can be lengthened without worrying about clock-skew. It requires a handshaking protocol with further requires an additional set of control lines.

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